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PD - 96187
IRFS3006-7PPBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
G S
VDSS 60V RDS(on) typ. 1.5m: max. 2.1m: ID (Silicon Limited) 293Ac ID (Package Limited) 240A
D
S G S S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
293c 207 240 1172 375 2.5 20 11 -55 to + 175
Units
A
c
d
W W/C V V/ns
f
300 10lbxin (1.1Nxm) 303 See Fig. 14, 15, 22a, 22b,
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
d
e
g jk
mJ A mJ
Thermal Resistance
Symbol
RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mount)
kl
Parameter
Typ.
--- ---
Max.
0.4 40
Units
C/W
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1
10/06/08
IRFS3006-7PPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG(int)
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
60 --- --- 2.0 --- --- --- ---
---
Conditions
--- 0.07 1.5 --- --- --- --- --- 2.1
--- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 5mAd 2.1 m VGS = 10V, ID = 168A 4.0 V VDS = VGS, ID = 250A VDS = 60V, VGS = 0V 20 A 250 VDS = 60V, VGS = 0V, TJ = 125C VGS = 20V 100 nA VGS = -20V -100
g
---
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
--- 200 37 60 140 14 61 118 69 8850 1007 525 1460 1915 --- 300 --- --- --- --- --- --- --- --- --- --- --- --- S
Conditions
290 --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)iA--- --- Effective Output Capacitance (Time Related)
h
VDS = 25V, ID = 168A ID = 168A VDS = 30V nC VGS = 10V ID = 168A, VDS =0V, VGS = 10V VDD = 39V ID = 168A ns RG = 2.7 VGS = 10V VGS = 0V VDS = 50V pF = 1.0MHz (See Fig 5) VGS = 0V, VDS = 0V to 48V VGS = 0V, VDS = 0V to 48V
g
g
i(See Fig 11) h
D
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Notes:
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ad Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 293 A 1172
Conditions
MOSFET symbol showing the integral reverse
G
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 168A, VGS = 0V TJ = 25C VR = 51V, --- 44 --- ns TJ = 125C IF = 168A --- 48 --- di/dt = 100A/s TJ = 25C --- 51 --- nC TJ = 125C --- 62 --- --- 2.03 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 240A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.021mH RG = 25, IAS = 168A, VGS =10V. Part not recommended for use above this value . ISD 168A, di/dt 1410 A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For
Coss while VDS is rising from 0 to 80% VDSS. recommended footprint and soldering techniquea refer to applocation note # AN-994 echniques refer to application note #AN-994. R is measured at TJ approximately 90C RJC value shown is at time zero
2
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IRFS3006-7PPBF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.0V 4.5V 4.0V 3.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.0V 4.5V 4.0V 3.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
3.5V 10
1
3.5V
60s PULSE WIDTH
Tj = 175C 1
60s PULSE WIDTH
Tj = 25C 0.1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 168A 2.0
ID, Drain-to-Source Current (A)
VGS = 10V
100
T J = 175C T J = 25C
10
1.5
1 VDS = 25V 60s PULSE WIDTH 2 3 4 5 6 7
1.0
0.1
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
16.0 ID= 168A
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
12.0
10000
Ciss Coss
VDS= 48V VDS= 30V
8.0
1000
Crss
4.0
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0.0 0 40 80 120 160 200 240 280 QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS3006-7PPBF
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000
100sec
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
T J = 175C
100
1msec
T J = 25C 10
10
LIMITED BY PACKAGE
10msec
DC 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 100
VGS = 0V 1.0 0.0 0.4 0.8 1.2 1.6 2.0 VSD, Source-to-Drain Voltage (V)
0.1 VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
350 Limited By Package 300
ID, Drain Current (A)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
80 Id = 5mA 75
250 200 150 100 50 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
70
65
60
55 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
2.5
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
1400 1200 1000 800 600 400 200 0 ID 35A 70A BOTTOM 168A TOP
2.0
Energy (J)
1.5
1.0
0.5
0.0 0 10 20 30 40 50 60
25
50
75
100
125
150
175
Fig 11. Typical COSS Stored Energy
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS3006-7PPBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
J R1 R1 J 1 2 R2 R2 R3 R3 3 R4 R4 C 1 2 3 4 4
Ri (C/W)
0.0062 0.0431 0.1462 0.2047
i (sec)
0.000005 0.000045 0.001067 0.010195
0.001
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1
0.0001 1E-006
1E-005
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 0.05 0.10
10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
350 300
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 168A
250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS3006-7PPBF
4.5
VGS(th), Gate threshold Voltage (V)
20
4.0 3.5
ID = 250A ID = 1.0mA ID = 1.0A
16
IF = 112A V R = 51V TJ = 25C TJ = 125C
2.5 2.0
IRR (A)
3.0
12
8
4
1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C )
0 0 200 400 600 800 1000 1200 diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
20 IF = 168A V R = 51V TJ = 25C TJ = 125C
QRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
600 500 400 300 200 IF = 112A V R = 51V TJ = 25C TJ = 125C
16
IRR (A)
12
8
4
100 0 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 diF /dt (A/s) diF /dt (A/s)
0
Fig. 18 - Typical Recovery Current vs. dif/dt
600 500 400
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 168A V R = 51V TJ = 25C TJ = 125C
300 200 100 0 0 200 400 600 800 1000 1200 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS3006-7PPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFS3006-7PPBF
D2Pak (TO-263CB) 7 Long Leads Package Outline
Dimensions are shown in milimeters (inches)
D2Pak - 7 Pin Part Marking Information
AIR
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
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IRFS3006-7PPBF
D2Pak - 7 Pin Tape and Reel
Dimensions are shown in milimeters (inches)
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2008
9

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